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february 2012 doc id 022771 rev 1 1/38 38 lnbh26 dual lnbs supply and control ic with step-up and i2c interface features complete interface between lnb and i2c bus built-in dc-dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.5 a) selectable output current limit by external resistor compliant with main satellite receivers output voltage specification (15 programmable levels) accurate built-in 22 khz tone generator suits widely accepted standards 22 khz tone waveform integrity guaranteed also at no load condition low drop post regulator and high efficiency step-up pwm with integrated power n-mos allowing low power losses lpm function (low power mode) to reduce dissipation overload and overtemperature internal protection with i2c diagnostic bits lnb short-circuit dynamic protection +/- 4 kv esd tolerant on output power pins applications stb satellite receivers tv satellite receivers pc card satellite receivers description intended for analog and digital dual satellite receivers/sat-tv, and sat-pc cards, the lnbh26 is a monolithic voltage regulator and interface ic, assembled in qfn24 4x4 specifically designed to provide the 13/18 v power supply and the 22 khz tone signalling to the lnb down-converter in the antenna dishes or to the multi-switch box. in this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and i2c standard interfacing. qfn24 (4 x 4 mm) table 1. device summary order code package packaging LNBH26PQR qfn24 (4 x 4) tape and reel www.st.com
contents lnbh26 2/38 doc id 022771 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 application information (valid for each section a/b) . . . . . . . . . . . . . . . 4 2.1 diseqc? data encoding (dsqin pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 data encoding by external 22 khz tone ttl signal . . . . . . . . . . . . . . . . . . 4 2.3 data encoding by external diseqc envelope control through the dsqin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 lpm (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 diseqc? 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 surge protections and tvs diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.10 flt: fault flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.11 vmon: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.12 tmon: 22 khz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.13 tdet: 22 khz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.14 imon: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.15 pdo: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8 2.16 power-on i2c interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8 2.17 png: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.18 isw: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.19 comp: boost capacitor esr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.20 olf: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9 2.21 otf: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
lnbh26 contents doc id 022771 rev 1 3/38 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 i2c interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
block diagram lnbh26 4/38 doc id 022771 rev 1 1 block diagram figure 1. block diagram am10475v1 voltage reference vup-b vout-b vcc sda scl gnd isel addr byp dsqin-a gate ctrl linear regulator isense pwm ctrl pgnd dac drop control tone ctrl diagnostics protections i2c digital core lx-b detin-b tone detector dsqout-b bpsw-b flt dsqin-b vup-a vout-a gate ctrl linear regulator isense pwm ctrl pgnd lx-a detin-a tone detector bpsw-a current limit selection dsqout-a
lnbh26 application information (valid for each section a/b) doc id 022771 rev 1 5/38 2 application information (valid for each section a/b) the lnbh26 includes two completely independent sections. except for isel, v cc and i2c inputs, each circuit can be separately controlled and have their independent external components. all the specifications below must be considered equal for both sections (a/b). this ic has a built-in dc-dc step-up converter that, from a single source (8 v to 16 v), generates the voltages (v up ) that let the integrated ldo post-regulator (generating the 13 v / 18 v lnb output voltages plus the 22 khz diseqc? tone) work with a minimum dissipated power of 0.5 w typ. @ 500 ma load (the ldo drop voltage is internally kept at v up - v out = 1 v typ.). the ldo power dissipation can be further reduced when 22 khz tone output is disabled by setting the lpm bit to ?1? (see lpm function description). the ic is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied v cc drops below a fixed threshold (4.7 v typ.). the step-up converter soft-start function reduces the in-rush current during startup. the ss time is internally fixed at 4 ms typ. to switch from 0 to 13 v, and 6 ms typ. to switch from 0 to 18 v. 2.1 diseqc? data encoding (dsqin pin) the internal 22 khz tone generator is factory trimmed in accordance with the diseqc? standards, and can be activated in 3 different ways: 1. by an external 22 khz source diseqc? data connected to the dsqin logic pin (ttl compatible). in this case the i2c tone control bits must be set: extm=ten=1. 2. by an external diseqc? data envelope source connected to the dsqin logic pin. in this case the i2c tone control bits must be set: extm=0 and ten=1. 3. through the ten i2c bit if the 22 khz presence is requested in continuous mode. in this case the dsqin ttl pin must be pulled high and the extm bit set to ?0?. each of the above solutions requires that during the 22 khz tone activation and/or diseqc? data transmission, the lpm bit must be set to ?0? [see 2.4: lpm (low power mode) ]. 2.2 data encoding by external 22 khz tone ttl signal in order to improve design flexibility an external tone signal can be input to the dsqin pin by setting the extm bit to ?1?. the dsqin is a logic input pin which activates the 22 khz tone to the v out pin, by using the lnbh26 integrated tone generator. the output tone waveforms are internally controlled by the lnbh26 tone generator in terms of rise/fall time and tone amplitude, while, the external 22 khz signal on the dsqin pin is used to define the frequency and the duty cycle of the output tone. a ttl compatible 22 khz signal is required for the proper control of the dsqin pin function. before sending the ttl signal on the dsqin pin, the extm and ten bits must be previously set to ?1?. as soon as the dsqin internal circuit detects the 22 khz ttl external signal code, the lnbh26 activates the 22 khz tone on the v out output with about 1 s delay from ttl signal activation, and it stops with about 60 s delay after the 22 khz ttl signal on dsqin has expired (refer to figure 2 ).
application information (valid for each section a/b) lnbh26 6/38 doc id 022771 rev 1 figure 2. tone enable and disable timing (using external waveform) 2.3 data encoding by external diseqc envelope control through the dsqin pin if an external diseqc? envelope source is available, it is possible to use the internal 22 khz generator activated during the tone transmission by connecting the diseqc? envelope source to the dsqin pin. in this case the i2c tone control bits must be set: extm=0 and ten=1. in this way the internal 22 khz signal is superimposed on the v out dc voltage to generate the lnb output 22 khz tone. during the period in which the dsqin is kept high the internal control circuit activates the 22 khz tone output. the 22 khz tone on the v out pin is activated with a delay of about 6 s from dsqin ttl signal rising edge, and it stops with a delay time in the range of 15 s to 60 s after the 22 khz ttl signal on dsqin has expired (refer to figure 3 ). figure 3. tone enable and disable timing (using envelope signal) 2.4 lpm (low power mode) in order to reduce total power loss, each section of the lnbh26 is provided with the lpm i2c bit that can be activated (lpm=1) in applications where the 22 khz tone can be disabled for long time periods. the lpm bit can be set to ?1? when the diseqc? data transmission is not requested (no 22 khz tone output is present); in this condition the drop voltage across the integrated ldo regulator (v up - v out ) is reduced to 0.6 v typ. and, consequently, the power loss inside the relative lnbh26 channel regulator is reduced too. for example, at 500 ma load, lpm=1, allowing a minimum ldo dissipated power of 0.3 w typ. it is recommended to set the lpm bit to ?0? before starting the 22 khz diseqc? data transmission; in this condition the drop voltage across the ldo is kept to 1 v typ. keep lpm=0 at all times in case the lpm function is not used. 2.5 diseqc? 2.0 implementation the built-in 22 khz tone detector completes the fully bi-directional diseqc? 2.0 interfacing. each lnbh26 section detin pin must be ac coupled to the diseqc? bus, and extracted pwk data is available on the corresponding dsqout pin. to comply with the bi-directional diseqc? 2.0 bus hardware requirements, an output r-l filter is needed (per each voltage am10426v1 ~ 1 s ~ 60 s dsqin tone output am10427v1 ~ 6 s 15 s ~ 60 s dsqin tone output
lnbh26 application information (valid for each section a/b) doc id 022771 rev 1 7/38 output pin). in order to avoid 22 khz waveform distortion during tone transmission, each lnbh26 section is provided with a bpsw pin to be connected to an external transistor, which allows the bypassing of the corresponding output rl filter in diseqc 2.x applications while in transmission mode. before starting tone transmission by means of the dsqin pin, provide that the ten bit is preventively set to ?1? and after ending tone transmission, provide that the ten bit is set to ?0?. 2.6 output current limit selection the linear regulators current limit threshold can be set by an external resistor connected to the isel pin. the resistor value defines the output current limit by the equation: equation 1 with iset=0 equation 2 with iset=1 (refer also to the iset bit description in ta b l e 9 .) where rsel is the resistor connected between isel and gnd expressed in k and i max (typ.) is the typical current limit threshold expressed in ma. i max can be set up to 1 a for each channel. however, it is recommended to not exceed, for a long period, a total amount of current of 1 a from both sections (i out_a + i out_b < 1 a) in order to avoid the overtemperature protection triggering and to thoroughly validate the pcb layout thermal management in real application environment conditions. 2.7 output voltage selection each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 + 4 bits of an internal data1 register (see section 7.3: data registers and table 14: output voltage selection table (data1 register, write mode) for exact programmable values). register writing is accessible via the i2c bus. 2.8 diagnostic and protection functions the lnbh26 has 14 diagnostic internal functions provided via the i2c bus, by reading 14 bits on two status registers (in read mode). all the diagnostic bits are, in normal operation (that is, no failure detected), set to low. one diagnostic bit is dedicated to the overtemperature status (otf), one bit is dedicated to the input voltage power not good function (png), while the remaining 12 bits (6 per channel) are dedicated to the overload 206 . 1 max rsel 16578 .) typ ( i = 159 . 1 max rsel 6452 .) typ ( i =
application information (valid for each section a/b) lnbh26 8/38 doc id 022771 rev 1 protection status (olf), to the output voltage level (vmon), to 22 khz tone characteristics (tmon), to the minimum load current (imon), to external voltage source presence on the v out pin (pdo), and to 22 khz tone presence on the detin pin (tdet). once the olf (or the otf or png) bit has been activated (set to ?1?), it is latched to ?1? until the relevant cause is removed and a new register reading operation is done. 2.9 surge protections and tvs diodes each lnbh26 device section is directly connected to the antenna cable in a set-top box. atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. this leads to currents or electromagnetic fields causing high voltage or current transients. transient voltage suppressor (tvs) devices are usually used, as shown in the following schematic ( figure 4 ), to protect each section of stb output circuits where the lnbh26 and other devices are electrically connected to the antenna cable. figure 4. surge protection circuit for this purpose we recommend the use of lnbtvsxx surge protection diodes specifically designed by st. the selection of the lnbtvs diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the lnbtvs datasheet for further details). 2.10 flt: fault flag in order to get an immediate feedback on a diagnostic status, the lnbh26 is equipped with a dedicated fault flag pin (flt). in the case an overload (olf bit=1), overheating (otf bit=1) or power not good (png bit=1) condition is detected, the flt pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. be aware that diagnostic bits olf, otf and png, once activated, are kept latched to ?1? until the origin cause is removed and a new register reading operation is performed by the microprocessor. the flt pin must be connected to a positive voltage (5 v max.) by means of a pull-up resistor. 2.11 vmon: output voltage diagnostic when one device output voltage is activated (v out pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, the relevant vmon i2c bit is set to ?1? (see ta b l e 1 7 for more details).
lnbh26 application information (valid for each section a/b) doc id 022771 rev 1 9/38 2.12 tmon: 22 khz tone diagnostic the 22 khz tone can be internally detected and monitored if one (or both) detin pin are connected to the lnb output bus (see figure 7 ) through a decoupling capacitor. the tone diagnostic function is provided with the corresponding tmon i2c bit. if the 22 khz tone amplitude and/or the tone frequency is out of the guaranteed limits (see ta bl e 1 9 ), the corresponding tmon i2c bit is set to ?1?. 2.13 tdet: 22 khz tone detection when a 22 khz tone presence is detected on one detin pin, the corresponding tdet i2c bit is set to ?1?. 2.14 imon: minimum output current diagnostic in order to detect the output load absence (no lnb connected on the bus or cable not connected to the ird) each lnbh26 section is provided with a minimum output current flag by the corresponding imon i2c bit, accessible in read mode, which is set to ?1? if the output current is lower than 12 ma (typ.). it is recommended to use the imon function only with the 22 khz tone transmission deactivated, otherwise the imon bit could be set to ?0? even if the output current is below the minimum current threshold. to activate the imon diagnostic function, set to ?1? the en_imon i2c bit in the data4 register. be aware that as soon as the imon function is activated by means of en_imon=1, the v out is immediately increased to 21 v (typ.) independently on the vsel bit setting. this operation is applied in order to be sure that the lnbh26 output has the higher voltage present in the lnb bus. do not use this function in an application environment where a 21 v voltage level is not supported by other peripherals connected to the lnb bus. 2.15 pdo: overcurrent detection on output pull-down stage when an overcurrent occurs on one section pull-down output stage due to an external voltage source greater than the lnbh26 nominal v out , and for a time longer than i sink_time_out (10 ms typ.), the corresponding pdo i2c bit is set to ?1?. this may happen due to an external voltage source presence on the lnb output (v out pin). for current threshold and deglitch time details, see ta b l e 1 3 . 2.16 power-on i2c interface reset and undervoltage lockout the i2c interface built into the lnbh26 is automatically reset at power-on. as long as the v cc stays below the undervoltage lockout (uvlo) threshold (4.7 v typ.), the interface does not respond to any i2c command and all data register bits are initialized to zeroes, therefore keeping the power blocks disabled. once the vcc rises above 4.8 v typ., the i2c interface becomes operative and the data registers can be configured by the main microprocessor.
application information (valid for each section a/b) lnbh26 10/38 doc id 022771 rev 1 2.17 png: input voltage minimum detection when input voltage (v cc pin) is lower than lpd (low power diagnostic) minimum thresholds, the png i2c bit is set to ?1? and the flt pin is set low. refer to ta b l e 3 for threshold details. 2.18 isw: inductor switching current limit in order to allow low saturation current inductors to be used, the maximum dc-dc inductor switching current limit threshold can be set by means of one i2c bit per section (isw). two values are available: 2.5 a typ. (with isw = 1) and 4 a typ. (with isw = 0). 2.19 comp: boost capacitor esr the dc-dc converter compensation loop can be optimized in order to work well with high or low esr capacitors (on the v up pin). for this purpose, one i2c bit in the data4 register (comp) can be set to ?1? or ?0?. it is recommended to reset this bit to ?0? unless using high esr capacitors. 2.20 olf: overcurrent and short-circuit protection and diagnostic in order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. it is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically by the corresponding pcl bit of the i2c data3 register. when the pcl (pulsed current limiting) bit is set lo low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for t on time (90 ms or 180 ms typ., according to the corresponding timer bit programmed in the data3 register) and after that, the output is set in shutdown for a t off time of typically 900 ms. simultaneously, the corresponding diagnostic olf i2c bit of the status1 register is set to ?1? and the flt pin is set to low level. after this time has elapsed, the involved output is resumed for a time t on . at the end of t on , if the overload is still detected, the protection circuit cycles again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low after register reading is done. typical t on +t off time is 990 ms (if timer=0) or 1080 ms (if timer=1) and is determined by an internal timer. this dynamic operation can greatly reduce the power dissipation in short- circuit condition, still ensuring excellent power-on startup in most conditions. however, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. this can be solved by initiating any power startup in static mode (pcl=1) and then, switching to dynamic mode (pcl=0) after a chosen amount of time, depending on the output capacitance. also in static mode, the diagnostic olf bit goes to ?1? (and the flt pin is set to low) when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is done. after the overload condition is removed, normal operation can be resumed in two ways, according to the olr i2c bit on the data4 register. if olr=1, all vsel bits corresponding to the involved section are reset to ?0? and the lnb section output (v out pin) is disabled. to re-enable the output stage, the vsel bits must be set again by the microprocessor and the olf bit is reset to ?0? after a register reading operation.
lnbh26 application information (valid for each section a/b) doc id 022771 rev 1 11/38 if olr=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and the olf bit is reset to ?0? after a register reading operation. 2.21 otf: thermal protection and diagnostic the lnbh26 is also protected against overheating: when the junction temperature exceeds 150 c (typ.), the step-up converter and both liner regulators are shut off, the diagnostic otf bit in the status1 register is set to ?1? and the flt pin is set to low level. after the overtemperature condition is removed, normal operation can be resumed in two ways, according to the therm i2c bit on the data4 register. if therm=1, all vsel bits are reset to ?0? and both lnb outputs (v out pins) are disabled. to re-enable output stages, the vsel bits must be set again by the microprocessor, while the otf bit is reset to ?0? after a register reading operation. if therm=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the otf bit is reset to ?0? after a register reading operation.
pin configuration lnbh26 12/38 doc id 022771 rev 1 3 pin configuration figure 5. pin connections (top view) am10476v1 gnd dsqout - a dsqin - b dsqin - a vup - a vcc pgnd flt lx - b lx -a sda isel detin - b vup - b detin -a vout - b nc vout -a dsqout -b byp bpsw - a addr bpsw -b scl 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 12 11 10 19 20 21 22 23 24 - - - - - - - 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 12 11 10 19 20 21 22 23 24 table 2. pin description pin symbol name pin function 1 dsqout-b diseqc output open drain output of channel a tone detector to the main microcontroller for diseqc 2.0 data decoding. it is low when tone is detected on the detin-b input pin. set to ground if not used. 2flt flt open drain output for ic fault conditions. it is set low in case of overload (olf bit) or overheating status (otf bit) or power not good (png bit) is detected. to be connected to pull-up resistor (5 v max.). 3 lx-a n-mos drain channel a, integrated n-channel power mosfet drain. 4 p-gnd power ground dc-dc converter power ground. to be connected directly to the exposed pad. 5 lx-b n-mos drain channel b, integrated n-channel power mosfet drain. 6 addr address setting tw o i 2 c bus addresses available by setting the address pin level voltage. see table 16 . 7 scl serial clock clock from i2c bus. 8 sda serial data bi-directional data from/to i2c bus. 9 isel current selection for both channel a and b the resistor ?rsel? connected between isel and gnd defines the linear regulator current limit threshold. refer to section 2.5 . also see the iset bit description in table 9 . the rsel resistor defines the same current limit both for channels a and b.
lnbh26 pin configuration doc id 022771 rev 1 13/38 pin symbol name pin function 10 v up-b channel b step-up voltage input of channel b linear post-regulator. the voltage on this pin is monitored by the internal channel b step-up controller to keep a minimum dropout across the linear pass transistor. 11 v out-b channel b, lnb output port output of channel b integrated very low drop linear regulator. see ta bl e 1 4 for voltage selection and description. 12 detin-b tone detector input channel b, 22 khz tone decoder input, must be ac coupled to the diseqc 2.0 bus. set to ground if not used. 13 bpsw-b switch control to be connected to an external transistor to be used to bypass the channel b output rl filter needed in diseqc 2.x applications during the diseqc transmitting mode (see section 5 ). set to ground if not used. open drain pin. 14 n.c. not internally connected not internally connected pin. set floating if not used. 15 gnd analog ground analog circuits ground. to be connected directly to the exposed pad. 16 byp bypass capacitor needed for internal pre-regulator filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. 17 v cc supply input 8 to 16 v ic dc-dc power supply. 18 bpsw-a switch control to be connected to an external transistor to be used to bypass the channel a output rl filter needed in diseqc 2.x applications during the diseqc transmitting mode (see section 5 ). set to ground if not used. open drain pin. 19 detin-a tone detector input channel a, 22 khz tone decoder input, must be ac coupled to the diseqc 2.0 bus. set to ground if not used. 20 v out-a channel a, lnb output port output of channel a integrated very low drop linear regulator. see ta bl e 1 4 for voltage selection and description. 21 v up-a channel a step-up voltage input of channel a linear post-regulator. the voltage on this pin is monitored by the internal channel a step-up controller to keep a minimum dropout across the linear pass transistor. 22 dsqin-a dsqin for diseqc envelope input or external 22 khz ttl input it is intended for channel a 22 khz tone control. it can be used as diseqc envelope input or external 22 khz ttl input depending on the extm-a i2c bit setting as follows: if extm-a=0, ten-a=1: it accepts the diseqc envelope code from the main microcontroller. the lnbh26 uses this code to modulate the internally generated 22 khz carrier. if extm-a=ten-a=1: it accepts external 22 khz logic signals which activate the 22 khz tone output (refer to section 2.2 ). pull up high if the tone output is activated only by the ten-a i2c bit. 23 dsqout-a diseqc output open drain output of channel a tone detector to the main microcontroller for diseqc 2.0 data decoding. it is low when tone is detected to the detin-a input pin. set to ground if not used. table 2. pin description (continued)
pin configuration lnbh26 14/38 doc id 022771 rev 1 pin symbol name pin function 24 dsqin-b dsqin for diseqc envelope input or external 22 khz ttl input it is intended for channel b 22 khz tone control. it can be used as diseqc envelope input or external 22 khz ttl input depending on the extm-b i2c bit setting as follows: if extm-b=0, ten-b=1: it accepts the diseqc envelope code from the main microcontroller. the lnbh26 uses this code to modulate the internally generated 22 khz carrier. if extm-a=ten-a=1: it accepts external 22 khz logic signals which activate the 22 khz tone output (refer to section 2.2 ). pull up high if the tone output is activated only by the ten-b i2c bit. epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat. table 2. pin description (continued)
lnbh26 maximum ratings doc id 022771 rev 1 15/38 4 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to network ground terminal. table 3. absolute maximum ratings symbol parameter value unit v cc dc power supply input voltage pins -0.3 to 20 v v up dc input voltage -0.3 to 40 v i out output current internally limited ma v out dc output pin voltage -0.3 to 40 v v i logic input pin voltage (sda, scl, dsqin, addr pins) -0.3 to 7 v v o logic output pin voltage (flt, dsqout) -0.3 to 7 v v bpsw bpsw pin voltage -0.3 to 40 v v detin detector input signal amplitude -0.6 to 2 v i o logic output pin current (flt, dsqout, bpsw) 10 ma lx lx input voltage -0.3 to 30 v v byp internal reference pin voltage -0.3 to 4.6 v isel current selection pin voltage -0.3 to 3.5 v t stg storage temperature range -50 to 150 c t j operating junction temperature range -25 to 125 c esd esd rating with human body model (hbm) for all pins, except power output pins 2 kv esd rating with human body model (hbm) for power output pins 4 table 4. thermal data symbol parameter value unit r thjc thermal resistance junction-case 2 c/w r thja thermal resistance junction-ambient with device soldered on 2s2p 4- layer pcb provided with thermal vias below exposed pad. 40 c/w
typical application circuits lnbh26 16/38 doc id 022771 rev 1 5 typical application circuits figure 6. diseqc 1.x application circuit table 5. diseqc 1.x bill of material (valid for a and b channels except for c1, c4, c7 and r1) component notes r1 (rsel) smd resistor. refer to ta bl e 1 3 and isel pin description in table 2 c1, c2 > 25 v electrolytic capacitor, 100 f is suitable c3 from 470 nf to 2.2 f ceramic capacitor. higher values allow lower dc-dc noise. c5 from 100 nf to 220 nf ceramic capacitor. higher values allow lower dc-dc noise. c4, c7 220 nf ceramic capacitors d1 stps130a or similar schottky diode d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, v rrm > 25 v, v f < 0 .5 v . to be placed as close as possible to v out pin d2 1n4001-07, s1a-s1m, or any similar general purpose rectifier l1 10 h inductor with i sat > i peak where i peak is the boost converter peak current am10477v1 c3-a vin 12v lnbout-a lx-a v up-a c4 lnbh26 d1-a c2-a c1 vcc byp c7 flt addr { i 2 c bus sda scl isel r1 (rsel) lx-b d1-b c2-b c3-b lnbout-b c5-b diseqc envelope ttl or diseqc 22khz ttl v up-b v out-b v out-a c5-a d2-a d2-b dsqin-a dsqin-b tone enable control 3 21 17 16 8 7 9 5 10 6 22 24 11 20 2 p-gnd a-gnd 4 15 d3-a d3-b l1-a l1-b
lnbh26 typical application circuits doc id 022771 rev 1 17/38 figure 7. diseqc 2.x application circuit table 6. diseqc 2.x bill of material (valid for a and b channels except for c1, c4, c7 and r1) component notes r1 (rsel) smd resistors. refer to ta bl e 1 3 and isel pin description in ta b l e 2 c1, c2 > 25 v electrolytic capacitor, 100 f is suitable c3 from 470 nf to 2.2 f ceramic capacitor. higher values allow lower dc-dc noise. c5 from 100 nf to 220 nf ceramic capacitor. higher values allow lower dc-dc noise. c4, c7 220 nf ceramic capacitors c6 10 nf ceramic capacitors d1 stps130a or similar schottky diode d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, v rrm >25 v, v f < 0 .5 v . to be placed as close as possible to v out pin d2 1n4001-07, s1a-s1m, or any similar general purpose rectifier l1 10 h inductor with i sat > i peak where i peak is the boost converter peak current l2 220 h inductor tr1 2str2160 or 2stf2340 or any small power pnp with ic > 250 ma, v ce > 30 v, can be used. also any small power pmos with id > 250 ma, r dson < 0.5 , v ds > 20 v, can be used. am1047 8 v1 l1-a c3-a vin 12v lnbout-a lx-a v up-a c4 lnbh26 d1-a c2-a c1 vcc d2-a byp c7 flt addr sda scl isel r1 (rsel) lx-b d1-b c2-b c3-b l1-b lnbout-b c5-b dsqout-a diseqc envelope ttl or diseqc 22khz ttl dsqin-a dsqin-b tone enable control v up-b v out-b bpsw-b dsqout-b d2-b v out-a c5-a bpsw-a 15 l2-a tr1-a 4.7k detin-a c6-a 15 l2-b tr1-b detin-b c6-b 4.7k flt open drains to controller { i 2 c bus 3 21 17 16 8 7 9 5 10 6 23 22 24 11 13 1 20 18 19 12 2 p-gnd a-gnd 4 15 d3-a d3-b 10k 4.7k 4.7k 10k
i2c bus interface lnbh26 18/38 doc id 022771 rev 1 6 i2c bus interface data transmission from the main microprocessor to the lnbh26 and vice versa takes place through the 2-wire i2c bus interface, consisting of the 2-line sda and scl (pull-up resistors to positive supply voltage must be externally connected). 6.1 data validity as shown in figure 8 , the data on the sda line must be stable during the high semi-period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 9 , a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 10 ). the peripheral (lnbh26) which acknowledges must pull down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed must generate acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the lnbh26 does not generate acknowledge if the v cc supply is below the undervoltage lockout threshold (4.7 v typ.). 6.5 transmission without acknowledge if detection of the acknowledge of the lnbh26 is not required, the microprocessor can use a simpler transmission: it simply waits one clock without checking the slave acknowledging, and sends the new data. this approach is of course less protected from misworking and decreases noise immunity.
lnbh26 i2c bus interface doc id 022771 rev 1 19/38 figure 8. data validity on the i2c bus figure 9. timing diagram of i2c bus figure 10. acknowledge on the i2c bus
i2c interface protocol lnbh26 20/38 doc id 022771 rev 1 7 i2c interface protocol 7.1 write mode transmission the lnbh26 interface protocol is made up of: a start condition (s) a chip address byte with the lsb bit r/w = 0 a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (p). the transfer lasts until a stop bit is encountered the lnbh25, as slave, acknowledges every byte transfer. figure 11. example of writing procedure starting with first data address 0x2 (a) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address (see ta b l e 1 6 for pin selection) and to select the register address (see ta bl e 7 to ta bl e 1 2 ). a. the writing procedure can start from any register address by simply setting the x values in the register address byte (after the chip address). it can be also stopped by the master by sending a stop condition after any acknowledge bit. am10479v1 s 000100x r/w = 0 ack 00000xxx ack vsel4-b vsel3-b vsel2-b vsel1-b vsel4-a vsel3-a vsel2-a vsel1-a ack msb lsb chip address msb lsb register address n/a extm-b lpm-b ten-b n/a extm-a lpm -a ten-a ack timer-b pcl-b isw-b iset-b timer-a pcl-a isw-a iset-a ack comp therm n/a en_imon-b olr n/a n/a en_imon-a ack p msb lsb msb lsb msb lsb msb lsb data 1 add=0x2 data 2 add=0x3 data 3 add=0x4 data 4 add=0x5
lnbh26 i2c interface protocol doc id 022771 rev 1 21/38 7.2 read mode transmission in read mode the bytes sequence must be as follows: a start condition (s) a chip address byte with the lsb bit r/w=0 the register address byte of the internal first register to be accessed a stop condition (p) a new master transmission with the chip address byte and the lsb bit r/w=1 after the acknowledge the lnbh26 starts to send the addressed register content. as long as the master keeps the acknowledge low, the lnbh26 transmits the next address register byte content. the transmission is terminated when the master sets the acknowledge high with a following stop bit. figure 12. example of reading procedure starting with first status address 0x0 (b) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address (see ta b l e 1 6 for pin selection) and to select the register address (see ta bl e 7 to ta bl e 1 2 ). b. the reading procedure can star t from any register address (status 1, 2 or data1..4) by simply setting the x values in the register address byte (after the first ch ip address in the above figur e). it can be also stopped by the master by sending a stop condition after any acknowledge bit. am104 8 0v1 s 000100x r/w = 0 ack 00000xxx ack p n/a n/a imon-b imon-a tmon-b tmon-a tdet-b tdet-a ack png otf pdo-b pdo-a vmon-b vmon-a olf-b olf-a ack msb lsb status 2 add=0x1 msb lsb status 1 add=0x0 s000100x r/w = 1 ack msb lsb chip address msb lsb register address msb lsb chip address vsel4-b vsel3-b vsel2-b vsel1-b vsel4-a vsel3-a vsel2-a vsel1-a ack n/a extm-b lpm-b ten-b n/a extm-a lpm -a ten-a ack timer-b pcl-b isw-b iset-b timer-a pcl-a isw-a iset-a ack comp therm n/a en_imon-b olr n/a n/a en_imon-a ack p msb lsb msb lsb msb lsb msb lsb data 1 add=0x2 data 2 add=0x3 data 3 add=0x4 data 4 add=0x5
i2c interface protocol lnbh26 22/38 doc id 022771 rev 1 7.3 data registers the data 1..4 registers can be addressed both in write and read mode. in read mode they return the last writing byte status received in the previous write transmission. the following tables provide the register address values of data 1..4 and a function description of each bit. n/a = reserved bit. all bits reset to ?0? at power-on. table 7. data 1 (read/write register. register address = 0x2) bit name ch value description bit 0 (lsb) vsel1-a a 0/1 channel a output voltage selection bits. (refer to ta bl e 1 4 ) bit 1 vsel2-a 0/1 bit 2 vsel3-a 0/1 bit 3 vsel4-a 0/1 bit 4 vsel1-b b 0/1 channel b output voltage selection bits. (refer to ta bl e 1 4 ) bit 5 vsel2-b 0/1 bit 6 vsel3-b 0/1 bit 7 (msb) vsel4-b 0/1
lnbh26 i2c interface protocol doc id 022771 rev 1 23/38 n/a = reserved bit. all bits reset to 0 at power-on. table 8. data 2 (read/write register. register address = 0x3) bit name ch value description bit 0 (lsb) ten-a a 1 22 khz tone enabled. tone output controlled by the dsqin pin 0 22 khz tone output disabled bit 1 lpm-a 1 low power mode activated (used only with 22 khz tone output disabled) 0 low power mode deactivated (keep always lpm=0 during 22 khz tone transmission) bit 2 extm-a 1 dsqin input pin is set to receive external 22 khz ttl signal source 0 dsqin input pin is set to receive external diseqc envelope ttl signal bit 3 n/a 0 reserved. keep to ?0? bit 4 ten-b b 1 22 khz tone enabled. tone output controlled by the dsqin pin 0 22 khz tone output disabled bit 5 lpm-b 1 low power mode activated (used only with 22 khz tone output disabled) 0 low power mode deactivated (keep always lpm=0 during 22 khz tone transmission) bit 6 extm-b 1 dsqin input pin is set to receive external 22 khz ttl signal source 0 dsqin input pin is set to receive external diseqc envelope ttl signal bit 7 (msb) n/a 0 reserved. keep to ?0?
i2c interface protocol lnbh26 24/38 doc id 022771 rev 1 n/a = reserved bit. all bits reset to 0 at power-on. table 9. data 3 (read/write register. register address = 0x4) bit name ch value description bit 0 (lsb) iset-a a 1 current limit of lnb output (vout pin) set to lower current range: refer to section 2.5 in application information section. 0 current limit of lnb output (vout pin) set to default range: refer to section 2.5 in application information section. bit 1 isw-a 1 dc-dc, inductor switching current limit set to 2.5 a typ. 0 dc-dc, inductor switching current limit set to 4 a typ. bit 2 pcl-a 1 pulsed (dynamic) lnb output current limiting is deactivated 0 pulsed (dynamic) lnb output current limiting is activated bit 3 timer-a 1 pulsed (dynamic) lnb output current t on time set to 180 ms typ. 0 pulsed (dynamic) lnb output current t on time set to 90 ms typ. bit 4 iset-b b 1 current limit of lnb output (v out pin) set to lower current range: refer to section 2.5 in the application information section. 0 current limit of lnb output (v out pin) set to default range: refer to section 2.5 in the application information section. bit 5 isw-b 1 dc-dc, inductor switching current limit set to 2.5 a typ. 0 dc-dc, inductor switching current limit set to 4 a typ. bit 6 pcl-b 1 pulsed (dynamic) lnb output current limiting is deactivated 0 pulsed (dynamic) lnb output current limiting is activated bit 7 (msb) timer-b 1 pulsed (dynamic) lnb output current t on time set to 180 ms typ. 0 pulsed (dynamic) lnb output current t on time set to 90 ms typ.
lnbh26 i2c interface protocol doc id 022771 rev 1 25/38 table 10. data 4 (read/write register. register address = 0x5) bit name ch value description bit 0 (lsb) en_imon- a a 1 imon diagnostic function is enabled . (v out is set to 21 v typ.) 0 imon diagnostic function is disabled. keep always at ?0? if imon is not used. bit 1 n/a 0 reserved. keep to ?0? bit 2 n/a 0 reserved. keep to ?0? bit 3 olr a/b 1 in the case of overload protection activation (olf=1), all vsel bits are reset to ?0? and lnb relevant output (v out pin) is disabled. the vsel bits must be set again by the master after the overcurrent condition is removed (olf=0). 0 in the case of overload protection activation (olf=1) the lnb output (v out pin) is automatically enabled as soon as the overload condition is removed (olf=0) with the previous vsel bit setting. bit 4 en_imon- b b 1 imon diagnostic function is enabled 0 imon diagnostic function is disabled. keep always at ?0? if imon is not used. bit 5 n/a 0 reserved. keep to ?0? bit 6 therm a/b 1 if thermal protection is activated (otf=1), all vsel bits are reset to ?0? and lnb output (v out pin) is disabled (both section a & b). the vsel bits must be set again by the master after the overtemperature condition is removed (otf=0). 0 in the case of thermal protection activation (otf=1) the lnb output (v out pin) is automatically enabled as soon as the overtemperature condition is removed (otf=0) with the previous vsel bit setting. bit 7 (msb) comp 1 dc-dc converter compensation set to use high e.s.r. capacitors (v up pin) 0dc - dc converter compensation set to use low e.s.r. capacitors (v up pin)
i2c interface protocol lnbh26 26/38 doc id 022771 rev 1 7.4 status registers the status 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables. n/a = reserved bit. all bits reset to 0 at power-on. table 11. status 1 (read register. register address = 0x0) bit name ch value description bit 0 (lsb) olf-a a 1 v out pin overload protection has been triggered (i out > i max ). refer to table 9 for the overload operation settings (iset, pcl, timer bits). 0 no overload protection has been triggered to v out pin (i out < i max ). bit 1 olf-b b 1 v out pin overload protection has been triggered (i out > i max ). refer to table 9 for the overload operation settings (iset, pcl, timer bits). 0 no overload protection has been triggered to v out pin (i out < i max ). bit 2 vmon-a a 1 output voltage (v out pin) lower than vmon specification thresholds. refer to ta bl e 1 7 . 0 output voltage (v out pin) is within the vmon specifications. bit 3 vmon-b b 1 output voltage (v out pin) lower than vmon specification thresholds. refer to ta bl e 1 7 . 0 output voltage (v out pin) is within the vmon specifications. bit 4 pdo-a a 1 overcurrent detected on output pull-down stage for a time longer than the deglitch period. this may happen due to an external voltage source present on the lnb output (v out pin). 0 no overcurrent detected on output pull-down stage. bit 5 pdo-b b 1 overcurrent detected on output pull-down stage for a time longer than the deglitch period. this may happen due to an external voltage source present on the lnb output (v out pin). 0 no overcurrent detected on output pull-down stage. bit 6 otf a/b 1 junction overtemperature is detected, t j > 150 c (typ.). see also the therm bit setting in ta bl e 1 0 . 0 junction overtemperature not detected, t j <135 c (typ.). t j is below thermal protection threshold. bit 7 (msb) png a/b 1 input voltage (v cc pin) lower than lpd minimum thresholds. refer to ta bl e 1 3 . 0 input voltage (v cc pin) higher than lpd thresholds. refer to ta bl e 1 3 .
lnbh26 i2c interface protocol doc id 022771 rev 1 27/38 n/a = reserved bit. all bits reset to 0 at power-on. table 12. status 2 (read register. register address = 0x1) bit name ch value description bit 0 (lsb) tdet-a a 1 22 khz tone presence is detected on the detin pin 0 no 22 khz tone is detected on the detin pin bit 1 tdet-b b 1 22 khz tone presence is detected on the detin pin 0 no 22 khz tone is detected on the detin pin bit 2 tmon-a a 1 22 khz tone present on the detin pin is out of tmon specification thresholds. that is: the tone frequency or the a tone (tone amplitude) are out of the thresholds guaranteed in ta bl e 1 9 . 0 22 khz tone present on the detin pin is within tmon specification thresholds. refer to ta bl e 1 9 . bit 3 tmon-b b 1 22 khz tone present on the detin pin is out of tmon specification thresholds. that is: the tone frequency or the a tone (tone amplitude) are out of the thresholds guaranteed in ta bl e 1 9 . 0 22 khz tone present on detin pin is within tmon specification thresholds. refer to ta bl e 1 9 . bit 4 imon-a a 1 output current (from v out pin) is lower than imon specification thresholds. refer to ta bl e 1 8 . 0 output current (from v out pin) is higher than imon specifications. refer to ta bl e 1 8 . bit 5 imon-b b 1 output current (from v out pin) is lower than imon specification thresholds. refer to ta bl e 1 8 . 0 output current (from v out pin) is higher than imon specifications. refer to ta bl e 1 8 . bit 6 n/a - reserved bit 7 (msb) n/a - reserved
electrical characteristics lnbh26 28/38 doc id 022771 rev 1 8 electrical characteristics refer to section 5 , t j from 0 to 85 c, all data 1..4 register bits set to 0 except vsel1 = 1, rsel = 11 k , dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the system register ( section 6 and section 7 ). table 13. electrical characteristics of section a/b symbol parameter test conditions min. typ. max. unit v in supply voltage (1) 81216v i in supply current both sections a and b enabled, i out = 0 ma 12 ma 22 khz tone enabled (ten-a/b = 1, dsqin-a/b = high), i out = 0 ma 19 both sections a and b set in standby: vsel1=vsel2=vsel3=vsel4=0 2 v out output voltage total accuracy valid at any v out selected level -3.5 +3.5 % v out line regulation v in = 8 to 16 v 40 mv v out load regulation i out from 50 to 750 ma 100 i max output current limiting thresholds rsel = 11 k , iset = 0 750 1100 ma rsel = 15 k , iset = 0 500 750 rsel = 20 k , iset = 0 350 550 i max output current limiting thresholds rsel = 11 k , iset = 1 400 ma rsel = 15 k , iset = 1 280 rsel = 20 k , iset = 1 200 i sc output short-circuit current rsel = 11 k , iset = 0 500 ma ss soft-start time v out from 0 to 13 v 4 ms ss soft-start time v out from 0 to 18 v 6 ms t13-18 soft transition rise time v out from 13 v to 18 v 1.5 ms t18-13 soft transition fall time v out from 18 v to 13 v 1.5 ms t off dynamic overload protection off time pcl = 0, output shorted 900 ms t on dynamic overload protection on time pcl = timer = 0, output shorted t off / 10 pcl = 0, timer = 1, output shorted t off / 5 a tone tone amplitude dsqin=high, extm=0, ten=1 i out from 0 to 750 ma c bus from 0 to 750 nf 0.55 0.675 0.8 v pp
lnbh26 electrical characteristics doc id 022771 rev 1 29/38 symbol parameter test conditions min. typ. max. unit f tone tone frequency dsqin=high, extm=0, ten=1 20 22 24 khz d tone tone duty cycle 43 50 57 % tr, tf tone rise or fall time (2) 5 8 15 s eff dc/dc dc-dc converter efficiency i out = 500 ma 93 % f sw dc-dc converter switching frequency 440 khz uvlo undervoltage lockout thresholds uvlo threshold rising 4.8 v uvlo threshold falling 4.7 v lp low power diagnostic (lpd) thresholds v lp threshold rising 7.2 v v lp threshold falling 6.7 v il dsqin, pin logic low 0.8 v v ih dsqin, pin logic high 2 v i ih dsqin, pin input current v ih = 5 v 15 a f detin tone detector frequency capture range 0.4 v pp sine wave (3) 19 22 25 khz v detin tone detector input amplitude sine wave signal, 22 khz 0.3 1.5 v pp z detin tone detector input impedance 150 k v ol dsqout, flt pins logic low detin tone present, i ol = 2 ma 0.3 0.5 v v ol_bps w bpsw pin low voltage i ol_bpsw = 5 ma dsqin = high, extm = 0, ten = 1 0.7 v i oz dsqout, flt pins leakage current detin tone absent, v oh = 6 v 10 a i obk output backward current all vselx = 0, v obk = 30 v -3 -6 ma i sink output low-side sink current v out forced at v out_nom +0.1 v 70 ma i sink_tim e-out low-side sink current time-out v out forced at v out_nom +0.1 v. pdo i2c bit is set to 1 after this time is elapsed. 10 ms i rev max. reverse current v out forced at v out_nom +0.1 v, after pdo bit is set to 1 (i sink_time- out elapsed). 2ma t shdn thermal shutdown threshold 150 c t shdn thermal shutdown hysteresis 15 c 1. in applications where (v cc - v out ) > 1.3 v, the increased power dissipation inside the integrated ldo must be taken into account in the application thermal management design. 2. guaranteed by design. 3. frequency range in which the detin function is guaranteed. the vpp level is intended on the lnb bus (before the c6 capacitor. see typical application circuit for diseqc 2.x) i out from 0 to 750 ma, c bus from 0 to 750 nf. table 13. electrical characteristics of section a/b (continued)
electrical characteristics lnbh26 30/38 doc id 022771 rev 1 8.1 output voltage selection each lnbh26 channel is provided with 15 output voltage levels (7 levels for 13 v range when vsel4-a/b=0 and 8 levels for 18 v range when vsel4-a/b=1) which can be selected through the register data1. ta b l e 1 4 shows the output voltage values corresponding to vselx bit combinations both for channel a and b. if all vselx are set to ?0? the device is set in standby mode and the vout-a/b is disabled. t j from 0 to 85 c, v i = 12 v. table 14. output voltage selection table (data1 register, write mode) (1) vsel4- a/b vsel3- a/b vsel2- a/b vsel1- a/b v out min. v out -a/b pin voltage v out max. function 0000 0 v out -a/b disabled. lnbh26 set in standby mode 000112.54513.00013.455 001012.86713.33313.800 001113.18813.66714.145 010013.5114.00014.490 010113.83214.33314.835 011014.15314.66715.180 011114.47515.00015.525 100017.51518.15018.785 100117.83618.48319.130 101018.15818.81719.475 101118.4819.15019.820 110018.80119.48320.165 110119.12319.81720.510 111019.44520.15020.855 111119.76620.48321.200 1. t j from 0 to 85 c, v i = 12 v. table 15. i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in input current sda, scl, v in = 0.4 to 4.5 v -10 10 a v ol low level output voltage (1) sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz 1. guaranteed by design.
lnbh26 electrical characteristics doc id 022771 rev 1 31/38 t j from 0 to 85 c, v i = 12 v. refer to section 5 , t j from 0 to 85 c, all data 1..4 register bits set to ?0?, rsel = 11 k , dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the system register. note: if the output voltage is lower than the min. value the vmon i2c bit is set to 1. if vmon=0 then v out > 80% of v out (typ.). if vmon=1 then v out < 95% of v out (typ.). refer to section 5 , t j from 0 to 85 c, rsel = 11 k , dsqin = low, v in = 12 v, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the system register. note: if the output current is lower than the min. threshold limit, the imon i2c bit is set to 1. if the output current is higher than the max. threshold limit, the imon i2c bit is set to 0. table 16. address pin characteristics symbol parameter test condition min. typ. max. unit v addr-1 ?0001000(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-2 ?0001001(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v table 17. output voltage diagnostic (vmon-a/b bits, status 1 register) characteristics symbol parameter test condition min. typ. max. unit v th-l diagnostic low threshold at v out = 13.0 v vsel1 = 1, vsel2 = vsel3 = vsel4 = 0 80 90 95 % v th-l diagnostic low threshold at v out = 18.15 v vsel4=1, vsel1 = vsel2 = vsel3 = 0 80 90 95 % table 18. output current diagnostic (imon-a/b bit, status 2 register) characteristics symbol parameter test condition min. typ. max. unit i th minimum current diagnostic threshold en_imon = 1 (v out is set to 21 v typ.) 5 12 20 ma
electrical characteristics lnbh26 32/38 doc id 022771 rev 1 refer to section 5 , t j from 0 to 85 c, all data 1..4 register bits set to ?0? except vsel1 = 1, ten=1, rsel = 11 k , dsqin = high, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the system register. note: if the 22 khz tone parameters are lower or higher than the above limits, the tmon i2c bit is set to ?1?. table 19. 22 khz tone diagnostic (tmon-a/b bit, status 2 register) characteristics symbol parameter test condition min. typ. max. unit a th-l amplitude diagnostic low threshold detin pin ac coupled 200 300 400 mv a th-h amplitude diagnostic high threshold detin pin ac coupled 900 1100 1200 mv f th-l frequency diagnostic low thresholds detin pin ac coupled 13 16.5 20 khz f th-h frequency diagnostic high thresholds detin pin ac coupled 24 29.5 38 khz
lnbh26 package mechanical data doc id 022771 rev 1 33/38 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 20. qfn24l (4 x 4 mm) mechanical data dim. (mm.) min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.55 2.70 2.80 e 3.90 4.00 4.10 e2 2.55 2.70 2.80 e 0.45 0.50 0.55 l 0.25 0.35 0.45
package mechanical data lnbh26 34/38 doc id 022771 rev 1 figure 13. qfn24l (4 x 4 mm) package dimensions 7596209_d
lnbh26 package mechanical data doc id 022771 rev 1 35/38 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
package mechanical data lnbh26 36/38 doc id 022771 rev 1 figure 14. qfn24l (4 x 4) footprint recommended data (mm.)
lnbh26 revision history doc id 022771 rev 1 37/38 10 revision history table 21. document revision history date revision changes 03-feb-2012 1 initial release.
lnbh26 38/38 doc id 022771 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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